1. Field of the Invention
The present invention relates to a semiconductor memory device having a nibble mode function, more particularly to a dynamic type random access memory (DRAM) having an improved nibble mode function.
2. Description of the Related Art
Recently, a DRAM having the nibble mode function has become widely used as a high speed access memory device. A feature of such a nibble mode function is to read data, for example, four bits of data, in parallel from a memory cell array in a read operation. In this case, a nibble mode cycle time has been already normalized and determined by a row address strobe signal and a nibble cycle of a column address strobe signal. That is, a column decoder is "set" or "reset" in response to a trailing or leading edge of the nibble cycle of the column address strobe signal. In this case, the read out data corresponding to a selected column decoder is stored temporarily in four latch means, for example, sense amplifiers. The latched data is sequentially read out through an output buffer means. In the nibble mode function, the latched data can be read at a high speed by "toggling" the column address strobe signal after one of the four latched data is first selected.
As explained above, the nibble mode cycle time is determined in correspondence with the cycle of the column address strobe signal and this cycle is normalized as a specification. In this case, the rise to a high level or the fall to a low level of a gate signal for the column decoder depends on the leading or trailing edge of the column address strobe signal.
Conventionally, in the nibble mode cycle time, the time for a read operation is sufficient, but the time for a write operation is short. This is because the column decoder is early set in order to quickly read out data, and reset in response to a next leading edge of the column address strobe signal. This insufficient write time, however, causes write errors to occur in the write operation.
These problems will be explained in detail hereinafter.